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ニューロンMOSFETを用いた多値ラッチ回路の高性能化
http://hdl.handle.net/10458/312
http://hdl.handle.net/10458/312ee533e1c-566d-4217-b3e0-4a5adb4ca41a
名前 / ファイル | ライセンス | アクション |
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KJ00002428233.pdf (468.6 kB)
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Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 2007-06-28 | |||||
タイトル | ||||||
言語 | ja | |||||
タイトル | ニューロンMOSFETを用いた多値ラッチ回路の高性能化 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Desigin of a Multiple-Valued Latch Circuit with high performance using Neuron MOSFETs | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | analog inverter, semi-froating gate, multiple-valued logic circuit, neuron MOSFET latch circuit | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
その他(別言語等)のタイトル | ||||||
その他のタイトル | ニューロン MOSFET オ モチイタ タチ ラッチ カイロ ノ コウセイノウカ | |||||
著者 |
中山, 悠
× 中山, 悠× 淡野, 公一× 石塚, 興彦× Nakayama, Yuu× Ishizuka, Okihiko |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Abstract A multiple-valued logic(MVL) circuit is a basic circuit which performs MVL digital processing. In this paper, a MVL latch circuit are presented, that holds a given MVL level. Originally, the MVL latch has been proposed by Mirmotahari, et. al. We improve it's characteristics with neuron MOSFETs. The noise margin is 30.0[m.V] compared with 48.0[mV] in the original circuits. |
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言語 | en | |||||
書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 33, p. 125-130, 発行日 2004-10 |
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出版者 | ||||||
言語 | ja | |||||
出版者 | 宮崎大学工学部 | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Faculty of Engineering, University of Miyazaki | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 05404924 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA00732558 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |