{"created":"2023-05-15T09:58:55.655271+00:00","id":2987,"links":{},"metadata":{"_buckets":{"deposit":"917b94f9-8b74-413e-bc31-70f55b2c8a98"},"_deposit":{"created_by":5,"id":"2987","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2987"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002987","sets":["73","73:36","73:36:330","73:36:330:314"]},"author_link":["15865","7152","12077","15868","12081"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"ニューロン MOSFET オ モチイタ タチ ラッチ カイロ ノ コウセイノウカ"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2004-10","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"130","bibliographicPageStart":"125","bibliographicVolumeNumber":"33","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Abstract \nA multiple-valued logic(MVL) circuit is a basic circuit which performs MVL digital processing. In this paper, \na MVL latch circuit are presented, that holds a given MVL level. Originally, the MVL latch has been proposed \nby Mirmotahari, et. al. We improve it's characteristics with neuron MOSFETs. The noise margin is 30.0[m.V] \ncompared with 48.0[mV] in the original circuits.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中山, 悠","creatorNameLang":"ja"},{"creatorName":"ナカヤマ, ユウ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"淡野, 公一","creatorNameLang":"ja"},{"creatorName":"タンノ, コウイチ","creatorNameLang":"ja-Kana"},{"creatorName":"Tanno, Koichi","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"石塚, 興彦","creatorNameLang":"ja"},{"creatorName":"イシズカ, オキヒコ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nakayama, Yuu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ishizuka, Okihiko","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00002428233.pdf","filesize":[{"value":"468.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00002428233.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2987/files/KJ00002428233.pdf"},"version_id":"37e625ba-0393-4bb4-8d24-d519795cd85b"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"analog inverter, semi-froating gate, multiple-valued logic circuit, neuron MOSFET latch circuit","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"ニューロンMOSFETを用いた多値ラッチ回路の高性能化","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ニューロンMOSFETを用いた多値ラッチ回路の高性能化","subitem_title_language":"ja"},{"subitem_title":"Desigin of a Multiple-Valued Latch Circuit with high performance using Neuron MOSFETs","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","314"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-06-28"},"publish_date":"2007-06-28","publish_status":"0","recid":"2987","relation_version_is_last":true,"title":["ニューロンMOSFETを用いた多値ラッチ回路の高性能化"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-30T00:14:36.686995+00:00"}