@article{oai:miyazaki-u.repo.nii.ac.jp:00002987,
 author = {中山, 悠 and 淡野, 公一 and Tanno, Koichi and 石塚, 興彦 and Nakayama, Yuu and Ishizuka, Okihiko},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Oct},
 note = {Abstract 
A multiple-valued logic(MVL) circuit is a basic circuit which performs MVL digital processing. In this paper, 
a MVL latch circuit are presented, that holds a given MVL level. Originally, the MVL latch has been proposed 
by Mirmotahari, et. al. We improve it's characteristics with neuron MOSFETs. The noise margin is 30.0[m.V] 
compared with 48.0[mV] in the original circuits.},
 pages = {125--130},
 title = {ニューロンMOSFETを用いた多値ラッチ回路の高性能化},
 volume = {33},
 year = {2004},
 yomi = {ナカヤマ, ユウ and タンノ, コウイチ and イシズカ, オキヒコ}
}