WEKO3
アイテム
ハイブリッドモードサーボ方式を用いた増幅回路のオフセット低減に関する研究
http://hdl.handle.net/10458/5888
http://hdl.handle.net/10458/5888c7107366-a731-4dec-8596-709ad0763b47
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
本文 (787.8 kB)
|
|
| Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2020-06-21 | |||||
| タイトル | ||||||
| タイトル | ハイブリッドモードサーボ方式を用いた増幅回路のオフセット低減に関する研究 | |||||
| 言語 | ja | |||||
| タイトル | ||||||
| タイトル | Research on Offset Reduction Technique Using Hybrid Mode Servo Method for Amplifiers | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | jpn | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | DC servo circuit, Operational Transconductance Amplifier (OTA), Offset Reduction, Attenuator | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | departmental bulletin paper | |||||
| 著者 |
宮田, 清也
× 宮田, 清也× 淡野, 公一× 田村, 宏樹× 外山, 貴子× Miyata, Seiya |
|||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | This thesis describes offset cancellation technique of CMOS amplifier for biological signal processing LSI. Our labratory try to develop the LSI for s-EMG (surface-Electromyogram). s-EMG has low-frequency and very small signal, so it needs to amplify for signal processing. But offset arises from mismatch caused by process variations, and it is very difficult to discriminate between s-EMG and offset. Thus biological signal processing LSI needs offset cancellation circuit to attenuate offset infection. DC servo circuit is one of the offset cancellation circuit. But DC servo circuit needs large passive component's value for low-frequency signal such as s-EMG. This causes an obstruction to integrate each circuit of biological signal processing LSI into one chip. To solve this problem, I propose hybrid mode servo circuit. This circuit's cut-off frequency (fc) can be lower by reducing transconductance (gm) of OTA used in integrator and increasing attenuation rate of attenuator. So this circuit can cancel offset without large passive component's value for low-frequency signal. The performance of the proposed circuit is evaluated through HSPICE simulation with 0.6μm CMOS device parameters. The simulation results are reported in this thesis. | |||||
| 言語 | en | |||||
| 書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 45, p. 153-158, 発行日 2016-07-29 |
|||||
| 出版者 | ||||||
| 出版者 | 宮崎大学工学部 | |||||
| 言語 | ja | |||||
| 出版者 | ||||||
| 出版者 | Faculty of Engineering, University of Miyazaki | |||||
| 言語 | en | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 05404924 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA00732558 | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
