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One-chip FPGA Implementation of Multi-Valued "And/Or"-Neural Network
http://hdl.handle.net/10458/262
http://hdl.handle.net/10458/262e174aea6-a106-43cf-af41-dd7a58a2123d
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
KJ00002425534.pdf (664.7 kB)
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| Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2007-06-28 | |||||
| タイトル | ||||||
| タイトル | One-chip FPGA Implementation of Multi-Valued "And/Or"-Neural Network | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | Neural network, FPGA, HDL, conclusive learning, disjunctive normal form, multi-dimensional exclusive OR, multi-valued logic, interpolation | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | departmental bulletin paper | |||||
| その他（別言語等）のタイトル | ||||||
| その他のタイトル | One-chip FPGA Implementation of Multi-Valued "And/Or"-Neural Network | |||||
| 言語 | en | |||||
| 著者 |
Wang, Kai
× Wang, Kai× Yuan, Yan× Wang, Qianyi× Aoyama, Tomoo |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Abstract To construct of a multi-layer network in a FPGA, we discuss simplified network constructions. We reexamined neuron functions for back-propagation learning. We made some improvements for the functions, but couldn't achieve drastic reduction. As the results, we abandoned back-propagation learning, and proposed a new neural network, named as AND/OR-neural network, which is derived from the disjunctive normal-form of logical expressions. The network is defined in the binary logic only and has a conclusive learning. The hardware amounts are less than that of the original, and the network can be implemented in a small size FPGA. However, the AND/OR-neural network has not prediction ability. Therefore, to obtain the ability, we expand it to multi-valued type. The extension is done approximately by replacements of logical operators. We discussed the property. We implemented the multi-valued AND/OR-network in 20K gates FPGA, and we could solve 7th-dimensional exclusive-OR problem in order of microsecond. |
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| 言語 | en | |||||
| 書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 32, p. 175-181, 発行日 2003-07 |
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| 出版者 | ||||||
| 出版者 | 宮崎大学工学部 | |||||
| 言語 | ja | |||||
| 出版者 | ||||||
| 出版者 | Faculty of Engineering, University of Miyazaki | |||||
| 言語 | en | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 05404924 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA00732558 | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
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Cite as
Wang, Kai, Yuan, Yan, Wang, Qianyi, Aoyama, Tomoo, 2003, One-chip FPGA Implementation of Multi-Valued "And/Or"-Neural Network: 宮崎大学工学部, 175–181 p.
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