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標準CMOSプロセスで製造可能な多値SRAMセルの設計
http://hdl.handle.net/10458/433
http://hdl.handle.net/10458/43340a8b296-628b-4ac0-9fda-c38f5780b403
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
KJ00004439508.pdf (713.3 kB)
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| Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2007-06-28 | |||||
| タイトル | ||||||
| タイトル | 標準CMOSプロセスで製造可能な多値SRAMセルの設計 | |||||
| 言語 | ja | |||||
| タイトル | ||||||
| タイトル | Design of Multiple-Valued SRAMs that can be Fabricated by Standard CMOS Process | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | jpn | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | SRAM, FG-MOSFET, Differential circuit, Quantization circuit | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | departmental bulletin paper | |||||
| その他（別言語等）のタイトル | ||||||
| その他のタイトル | ヒョウジュン CMOS プロセス デ セイゾウ カノウナ タチ SRAM セル ノ セッケイ | |||||
| 言語 | ja-Kana | |||||
| 著者 |
山下, 崇
× 山下, 崇× 淡野, 公一× 外山, 貴子× Yamashita, Takashi |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Abstract In this paper, we propose four kinds of multiple-valued SRAM cells can be fa bricated in the standard CMOS process. At first, a multiple-valued SRAM cell only using N-channel MOSFETS is presented. Because P-channel MOSFETs are not used in the SRAM cell, the chip area can be reduced. Next, a multiple-v alued SRAM cell with differential circuits is presented. Because the cell i s realized using the current-mode inside the cell, multiple thresholds can b e obtained by connecting the wires. The third SRAM cell is the circuit cons titution that combined MOSFET with FG-MOSFET. This is realized by using the characteristics of the variable threshold voltage in FG-MOSFETs. The last circuit is a circuit composition that uses the quantization circuit, and has a high noise margin and a switching sensitivity can be achieved. Because a special fabrication process is not required for realizing all the proposed SRAM cells, they can be achieved at a low cost. The proposed multiple-val ued SRAM cells are designed with a 0.35mum CMOS device parameter, and eval uate through HSPICE simulation. As a result, it was confirmed that four pro posal circuits operated as multiple-valued SRAM cells. |
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| 言語 | en | |||||
| 書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 35, p. 177-184, 発行日 2006-08-30 |
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| 出版者 | ||||||
| 出版者 | 宮崎大学工学部 | |||||
| 言語 | ja | |||||
| 出版者 | ||||||
| 出版者 | Faculty of Engineering, University of Miyazaki | |||||
| 言語 | en | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 05404924 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA00732558 | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
