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クロックフィールドスルーとチャネル長変調効果を補償したスイッチドボルテージ サンプル/ホールド回路
http://hdl.handle.net/10458/364
http://hdl.handle.net/10458/36445f5cd9f-5d57-4394-b24e-3dae6a07e5a3
名前 / ファイル | ライセンス | アクション |
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KJ00003579355.pdf (393.1 kB)
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Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 2007-06-28 | |||||
タイトル | ||||||
言語 | ja | |||||
タイトル | クロックフィールドスルーとチャネル長変調効果を補償したスイッチドボルテージ サンプル/ホールド回路 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Switched-Voltage Sample/Hold Circuit compensated for Clock Feedthrough and Channel-Length Modulation Effect | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | switched-voltage, delay cell, clock feedthrough, channel-length modulation effect | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
その他(別言語等)のタイトル | ||||||
その他のタイトル | クロックフィールド スルー ト チャネルチョウ ヘンチョウ コウカ オ ホショウ シタ スイッチド ボルテージ サンプル ホールド カイロ | |||||
言語 | ja-Kana | |||||
著者 |
大野, 憲司
× 大野, 憲司× 松本, 寛樹× 村尾, 健次× 村尾, 健次 |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Abstract In this paper, swicthed-voltage (SV) sample/hold (S/H) circuit are presented to compensated for clock feedthouh(CFT) and channel-length modulation effect. The circuit consists of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuit can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice. |
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言語 | en | |||||
書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 34, p. 43-46, 発行日 2005-08 |
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出版者 | ||||||
言語 | ja | |||||
出版者 | 宮崎大学工学部 | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Faculty of Engineering, University of Miyazaki | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 05404924 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA00732558 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |