@article{oai:miyazaki-u.repo.nii.ac.jp:00002391,
 author = {大野, 憲司 and Ohno, Kenji and 松本, 寛樹 and Matsumoto, Hiroki and 村尾, 健次 and Murao, Kenji and 村尾, 健次 and Murao, Kenji},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Aug},
 note = {Abstract 
In this paper, swicthed-voltage (SV) sample/hold (S/H) circuit are presented to compensated 
for clock feedthouh(CFT) and channel-length modulation effect. The circuit consists of a CMOS 
SV-delay cell. Thus, the configuration is very simple. The proposed circuit can be operated using 
simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.},
 pages = {43--46},
 title = {クロックフィールドスルーとチャネル長変調効果を補償したスイッチドボルテージ サンプル/ホールド回路},
 volume = {34},
 year = {2005},
 yomi = {オオノ, ケンジ and マツモト, ヒロキ and ムラオ, ケンジ and ムラオ, ケンジ}
}