{"created":"2023-05-15T09:58:54.461562+00:00","id":2965,"links":{},"metadata":{"_buckets":{"deposit":"4603c474-6a3e-476f-845f-4e9323047349"},"_deposit":{"created_by":5,"id":"2965","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2965"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002965","sets":["73","73:36","73:36:330","73:36:330:321"]},"author_link":["15707","11928","15709","12742"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"3ソウ クロック オ モチイタ ヨウリョウヒ テイゲンガタ タンイツ リトク ゾウフクキ コウセイ SC セキブンキ"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-07-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"113","bibliographicPageStart":"111","bibliographicVolumeNumber":"40","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this study, a capacitance ratio-reduced and unity gain buffer-based switched-capacitor integrator using three phase clocks is presented. Principle of operation is described and is also confirmed on SIMetrix. The purpose of this proposal circuit is to decrease the capacitor ratio of the SC integrator, and to improve the maximum frequency that can operate. Very large capacitance ratio is derived.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"黒木, 伸一","creatorNameLang":"ja"},{"creatorName":"クロキ, シンイチ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"松本, 寛樹","creatorNameLang":"ja"},{"creatorName":"マツモト, ヒロキ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kuroki, Shinichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Matumoto, Hiroki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"21engineering40_pp.111-113.pdf","filesize":[{"value":"247.2 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"21engineering40_pp.111-113.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2965/files/21engineering40_pp.111-113.pdf"},"version_id":"b8500262-b9f1-4576-93ad-d4d3266c4ad5"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Three phase clocks, SC integrator, Capacitance ratio","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"3相クロックを用いた容量比低減型単一利得増幅器構成SC積分器","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"3相クロックを用いた容量比低減型単一利得増幅器構成SC積分器","subitem_title_language":"ja"},{"subitem_title":"Capacitance ratio-reduced and unity gain buffer-based SC integrator using three phase clocks","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","321"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2012-03-09"},"publish_date":"2012-03-09","publish_status":"0","recid":"2965","relation_version_is_last":true,"title":["3相クロックを用いた容量比低減型単一利得増幅器構成SC積分器"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-30T05:15:19.179757+00:00"}