{"created":"2023-05-15T09:58:53.053491+00:00","id":2936,"links":{},"metadata":{"_buckets":{"deposit":"49db7a3d-24cb-457d-8d5f-37e6b1f29bf1"},"_deposit":{"created_by":5,"id":"2936","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2936"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002936","sets":["73","73:36","73:36:330","73:36:330:319"]},"author_link":["11805","15559","11807","15562"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"ジリツ コショウ ホショウ カノウ ナ ニューロン ノ フォワード・パス ブ ノ セッケイ ト FPGA ジョウ エノ ジッソウ"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009-09-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"354","bibliographicPageStart":"349","bibliographicVolumeNumber":"38","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Larning time of large-scale neural network is a serious problem. To achieve fast learning, some researchers proposed to implement a neural networks into Wafer Scale Integration(WSI). When neural networks is implemented into a WSI, it has to have a mechanism to compensate defect or fault. Partial Retraining(PR) scheme was proposed as one of the methods of compensating for hardware defects. However, PR scheme does not evaluate its performance on the hardware still yet. In this paper, we implement a forward pass of PR scheme into a Field Programmable Gate Array(FPGA) and test its functions.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山森, 一人","creatorNameLang":"ja"},{"creatorName":"ヤマモリ, クニヒト","creatorNameLang":"ja-Kana"},{"creatorName":"Yamamori, Kunihito","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"草野, 真道","creatorNameLang":"ja"},{"creatorName":"クサノ, マサミチ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉原, 郁夫","creatorNameLang":"ja"},{"creatorName":"ヨシハラ, イクオ","creatorNameLang":"ja-Kana"},{"creatorName":"Yoshihara, Ikuo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kusano, Masamiti","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00005633799.pdf","filesize":[{"value":"3.3 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00005633799.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2936/files/KJ00005633799.pdf"},"version_id":"d3c98659-47ec-4fdb-874a-0491037f3de5"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Partial Retraining scheme, FPGA, neural network, fault-tolerance","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"自律故障補償可能なニューロンのフォワード・パス部の設計とFPGA上への実装","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"自律故障補償可能なニューロンのフォワード・パス部の設計とFPGA上への実装","subitem_title_language":"ja"},{"subitem_title":"Design and Implementation of Self Defect Compensatable Neuron on FPGA device","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","319"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2009-10-30"},"publish_date":"2009-10-30","publish_status":"0","recid":"2936","relation_version_is_last":true,"title":["自律故障補償可能なニューロンのフォワード・パス部の設計とFPGA上への実装"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-30T03:00:48.489891+00:00"}