@article{oai:miyazaki-u.repo.nii.ac.jp:00002936,
 author = {山森, 一人 and Yamamori, Kunihito and 草野, 真道 and 吉原, 郁夫 and Yoshihara, Ikuo and Kusano, Masamiti},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Sep},
 note = {Larning time of large-scale neural network is a serious problem. To achieve fast learning, some researchers proposed to implement a neural networks into Wafer Scale Integration(WSI). When neural networks is implemented into a WSI, it has to have a mechanism to compensate defect or fault. Partial Retraining(PR) scheme was proposed as one of the methods of compensating for hardware defects. However, PR scheme does not evaluate its performance on the hardware still yet. In this paper, we implement a forward pass of PR scheme into a Field Programmable Gate Array(FPGA) and test its functions.},
 pages = {349--354},
 title = {自律故障補償可能なニューロンのフォワード・パス部の設計とFPGA上への実装},
 volume = {38},
 year = {2009},
 yomi = {ヤマモリ, クニヒト and クサノ, マサミチ and ヨシハラ, イクオ}
}