{"created":"2023-05-15T09:58:48.682592+00:00","id":2835,"links":{},"metadata":{"_buckets":{"deposit":"6d69de78-9295-4034-95e4-83f75f1f5636"},"_deposit":{"created_by":5,"id":"2835","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2835"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002835","sets":["73","73:36","73:36:330","73:36:330:323"]},"author_link":["7152","12078","7150","14948"],"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2013-08-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"126","bibliographicPageStart":"121","bibliographicVolumeNumber":"42","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter. The proposed MVL inverter and inverted MVL hysteresis comparator are expandable, capable to use more numbers of levels in MVL circuits. The performances of all proposed MVL circuits were evaluated through HSPICE with the set of 0.18μm CMOS process parameters. From the simulation results, we could confirm that all proposed MVL circuits work well as theory.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Mannan, Arif Abdul","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"14948","nameIdentifierScheme":"WEKO"}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"0000000106573887","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"https://isni.org/isni/0000000106573887"}],"affiliationNames":[{"affiliationName":"宮崎大学","affiliationNameLang":"ja"},{"affiliationName":"University of Miyazaki","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"田村, 宏樹","creatorNameLang":"ja"},{"creatorName":"タムラ, ヒロキ","creatorNameLang":"ja-Kana"},{"creatorName":"Tamura, Hiroki","creatorNameLang":"en"}],"familyNames":[{"familyName":"田村","familyNameLang":"ja"},{"familyName":"タムラ","familyNameLang":"ja-Kana"},{"familyName":"Tamura","familyNameLang":"en"}],"givenNames":[{"givenName":"宏樹","givenNameLang":"ja"},{"givenName":"ヒロキ","givenNameLang":"ja-Kana"},{"givenName":"Hiroki","givenNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"7150","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"90334713","nameIdentifierScheme":"e-Rad_Researcher","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=90334713"}]},{"creatorNames":[{"creatorName":"Toyama, Takako","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"12078","nameIdentifierScheme":"WEKO"}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"0000000106573887","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"https://isni.org/isni/0000000106573887"}],"affiliationNames":[{"affiliationName":"宮崎大学","affiliationNameLang":"ja"},{"affiliationName":"University of Miyazaki","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"淡野, 公一","creatorNameLang":"ja"},{"creatorName":"タンノ, コウイチ","creatorNameLang":"ja-Kana"},{"creatorName":"Tanno, Koichi","creatorNameLang":"en"}],"familyNames":[{"familyName":"淡野","familyNameLang":"ja"},{"familyName":"タンノ","familyNameLang":"ja-Kana"},{"familyName":"Tanno","familyNameLang":"en"}],"givenNames":[{"givenName":"公一","givenNameLang":"ja"},{"givenName":"コウイチ","givenNameLang":"ja-Kana"},{"givenName":"Koichi","givenNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"7152","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"50260740","nameIdentifierScheme":"e-Rad_Researcher","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=50260740"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"engineering121-126.pdf","filesize":[{"value":"866.9 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"engineering121-126.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2835/files/engineering121-126.pdf"},"version_id":"c3bc2969-47b6-4df5-a899-bf4c0220fdd5"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Multiple-Valued Logic, Inverter, Threshold Detector, Hysteresis Comparator","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","323"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2013-12-26"},"publish_date":"2013-12-26","publish_status":"0","recid":"2835","relation_version_is_last":true,"title":["Expandable MVL CMOS Inverter and Its Application to MVL CMOS Hysteresis Comparator without Backgate Scheme"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2024-12-26T07:33:56.473399+00:00"}