{"created":"2023-05-15T09:58:36.025625+00:00","id":2585,"links":{},"metadata":{"_buckets":{"deposit":"23e1b66a-dcfe-42aa-aabf-d1e2d58e90e5"},"_deposit":{"created_by":5,"id":"2585","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2585"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002585","sets":["73","73:36","73:36:330","73:36:330:313"]},"author_link":["13279","13280","13281","13282"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"One-chip FPGA Implementation of Multi-Valued \"And/Or\"-Neural Network","subitem_alternative_title_language":"en"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2003-07","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"181","bibliographicPageStart":"175","bibliographicVolumeNumber":"32","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Abstract \nTo construct of a multi-layer network in a FPGA, we discuss simplified network constructions. We \nreexamined neuron functions for back-propagation learning. We made some improvements for the \nfunctions, but couldn't achieve drastic reduction. As the results, we abandoned back-propagation \nlearning, and proposed a new neural network, named as AND/OR-neural network, which is derived \nfrom the disjunctive normal-form of logical expressions. The network is defined in the binary logic \nonly and has a conclusive learning. The hardware amounts are less than that of the original, and the \nnetwork can be implemented in a small size FPGA. However, the AND/OR-neural network has not \nprediction ability. Therefore, to obtain the ability, we expand it to multi-valued type. The extension is \ndone approximately by replacements of logical operators. We discussed the property. We \nimplemented the multi-valued AND/OR-network in 20K gates FPGA, and we could solve \n7th-dimensional exclusive-OR problem in order of microsecond.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Wang, Kai","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13279","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yuan, Yan","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13280","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Wang, Qianyi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13281","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Aoyama, Tomoo","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"13282","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00002425534.pdf","filesize":[{"value":"664.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00002425534.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2585/files/KJ00002425534.pdf"},"version_id":"929cb686-6408-4294-a5cf-32d62064d0a4"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Neural network, FPGA, HDL, conclusive learning, disjunctive normal form, multi-dimensional exclusive OR, multi-valued logic, interpolation","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"One-chip FPGA Implementation of Multi-Valued \"And/Or\"-Neural Network","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"One-chip FPGA Implementation of Multi-Valued \"And/Or\"-Neural Network","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","313"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-06-28"},"publish_date":"2007-06-28","publish_status":"0","recid":"2585","relation_version_is_last":true,"title":["One-chip FPGA Implementation of Multi-Valued \"And/Or\"-Neural Network"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-29T23:59:10.036293+00:00"}