@article{oai:miyazaki-u.repo.nii.ac.jp:00002529,
 author = {大野, 憲司 and Ohno, Kenji and 松本, 寛樹 and Matsumoto, Hiroki and 村尾, 健次 and Murao, Kenji and 村尾, 健次 and Murao, Kenji},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Aug},
 note = {In this paper, switched-voltage (SV) sample/hold (S/H) circuit is presented for low voltage operation. The circuit consists of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuit can operate using simple nonoverlapping two phase clocks. Performance is estimated by simulations on PSpice.},
 pages = {165--168},
 title = {高精度低電圧スイッチトボルテージサンプルホールド回路},
 volume = {36},
 year = {2007},
 yomi = {オオノ, ケンジ and マツモト, ヒロキ and ムラオ, ケンジ and ムラオ, ケンジ}
}