{"created":"2023-05-15T09:58:32.373109+00:00","id":2511,"links":{},"metadata":{"_buckets":{"deposit":"26a3a8f5-4631-4e4f-86ce-8b9e886bddcc"},"_deposit":{"created_by":5,"id":"2511","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2511"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002511","sets":["73","73:36","73:36:330","73:36:330:317"]},"author_link":["12813","7152","7150","12078","12817"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"デンリュウ モード MVD-ORNS ノ テイショウヒ デンリョクカ ニ カンスル コウサツ","subitem_alternative_title_language":"ja-Kana"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2007-08-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"56","bibliographicPageStart":"49","bibliographicVolumeNumber":"36","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Recently, advanced digital signal processing is necessary so that industry related to multimedia may develop. Because many arithmetic circuits are used in signal processing of the multimedia, a low-power and high-speed adder, which is basic element of the arithmetic circuits, are desired. On the other hand, multiple-valued digits overlap resolution number system (MVD-ORNS) was proposed in our lab, and is one of the number systems that make it possible to add in parallel. However, the hardware of MVD-ORNS consumes very large power. In this thesis, I design and analyze the very low-power MOS circuit elements, which are current-mirrors, switched current mirrors, etc. based on the weakinversion region, for the low-power MVD-ORNS. Finally, an 8-bit adder based on MVD-ORNS using the proposed circuits is designed. All of the proposed circuits are evaluated through HSPICE simulation with 0.35μm CMOS device parameters. The results are reported in this thesis.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"澤田, 良太","creatorNameLang":"ja"},{"creatorName":"サワダ, リョウタ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"淡野, 公一"},{"creatorName":"タンノ, コウイチ","creatorNameLang":"ja-Kana"},{"creatorName":"Tanno, Koichi","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"田村, 宏樹","creatorNameLang":"ja"},{"creatorName":"タムラ, ヒロキ","creatorNameLang":"ja-Kana"},{"creatorName":"Tamura, Hiroki","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"外山, 貴子","creatorNameLang":"ja"},{"creatorName":"トヤマ, タカコ","creatorNameLang":"ja-Kana"},{"creatorName":"Toyama, Takako","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Sawada, Ryota","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00004682866.pdf","filesize":[{"value":"1.0 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00004682866.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2511/files/KJ00004682866.pdf"},"version_id":"1dd3a343-f41f-4cf8-a9b2-d22d9a64723a"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"MVD-ORNS, Current-Mode, low-power, current-mirrors","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"電流モードMVD-ORNSの低消費電力化に関する考察","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"電流モードMVD-ORNSの低消費電力化に関する考察","subitem_title_language":"ja"},{"subitem_title":"A Discussion on Reduction of Power Consumption for Current-Mode MVD-ORNS","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","317"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-10-30"},"publish_date":"2007-10-30","publish_status":"0","recid":"2511","relation_version_is_last":true,"title":["電流モードMVD-ORNSの低消費電力化に関する考察"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-29T23:37:21.770427+00:00"}