@article{oai:miyazaki-u.repo.nii.ac.jp:00002511,
 author = {澤田, 良太 and 淡野, 公一 and Tanno, Koichi and 田村, 宏樹 and Tamura, Hiroki and 外山, 貴子 and Toyama, Takako and Sawada, Ryota},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Aug},
 note = {Recently, advanced digital signal processing is necessary so that industry related to multimedia may develop. Because many arithmetic circuits are used in signal processing of the multimedia, a low-power and high-speed adder, which is basic element of the arithmetic circuits, are desired. On the other hand, multiple-valued digits overlap resolution number system (MVD-ORNS) was proposed in our lab, and is one of the number systems that make it possible to add in parallel. However, the hardware of MVD-ORNS consumes very large power. In this thesis, I design and analyze the very low-power MOS circuit elements, which are current-mirrors, switched current mirrors, etc. based on the weakinversion region, for the low-power MVD-ORNS. Finally, an 8-bit adder based on MVD-ORNS using the proposed circuits is designed. All of the proposed circuits are evaluated through HSPICE simulation with 0.35μm CMOS device parameters. The results are reported in this thesis.},
 pages = {49--56},
 title = {電流モードMVD-ORNSの低消費電力化に関する考察},
 volume = {36},
 year = {2007},
 yomi = {サワダ, リョウタ and タンノ, コウイチ and タムラ, ヒロキ and トヤマ, タカコ}
}