{"created":"2023-05-15T09:58:31.467876+00:00","id":2494,"links":{},"metadata":{"_buckets":{"deposit":"985b446c-be5e-41ab-83bf-b8eb57f6b899"},"_deposit":{"created_by":5,"id":"2494","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2494"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002494","sets":["73","73:36","73:36:330","73:36:330:320"]},"author_link":["12687","12684","11805","11807"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"ジリツ コショウ ホショウ カノウ ナ ハードウェア ニューロン ノ バックワード パス エンサンブ ノ セッケイ","subitem_alternative_title_language":"ja-Kana"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2010-09-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"344","bibliographicPageStart":"339","bibliographicVolumeNumber":"39","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In neural network, there is a problem that learning time becomes so long for real world problems. To achieve fast learning, some researchers proposed to implement a neural network into a Wafer Scale Integration (WSI). WSI uses one wafer as a parallel computer, a part of defect leads entire system fault. Therefore a defect compensation method is necessary to implement a neural network into WSI. Partial Retraining (PR) scheme has proposed as one of the defect compensation methods for neural networks. However, PR scheme is not verified whether it will perform good on hardware devices or not. It is also not clear how much is circuit required. In our laboratory, we have been finished a design of forward-pass module of self-defect-compensatable hardware neuron. In this paper, we report a design of backward-pass module, and evaluate the performance of our design by simulations.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"0000000106573887","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"https://isni.org/isni/0000000106573887"}],"affiliationNames":[{"affiliationName":"宮崎大学","affiliationNameLang":"ja"},{"affiliationName":"University of Miyazaki","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"山森, 一人","creatorNameLang":"ja"},{"creatorName":"ヤマモリ, クニヒト","creatorNameLang":"ja-Kana"},{"creatorName":"Yamamori, Kunihito","creatorNameLang":"en"}],"familyNames":[{"familyName":"山森","familyNameLang":"ja"},{"familyName":"ヤマモリ","familyNameLang":"ja-Kana"},{"familyName":"Yamamori","familyNameLang":"en"}],"givenNames":[{"givenName":"一人","givenNameLang":"ja"},{"givenName":"クニヒト","givenNameLang":"ja-Kana"},{"givenName":"Kunihito","givenNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"11805","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"50293395","nameIdentifierScheme":"e-Rad_Researcher","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=50293395"}]},{"creatorNames":[{"creatorName":"田代, 圭佑"},{"creatorName":"タシロ, ケイスケ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"12684","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"吉原, 郁夫","creatorNameLang":"ja"},{"creatorName":"ヨシハラ, イクオ","creatorNameLang":"ja-Kana"},{"creatorName":"Yoshihara, Ikuo","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"11807","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Tashiro, Keisuke","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"12687","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"engineering39-52.pdf","filesize":[{"value":"921.9 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"engineering39-52.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2494/files/engineering39-52.pdf"},"version_id":"0f876e90-35f4-4e72-b8dc-4f378becbff0"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Partial Retraining scheme, Neural network, Defect compensation, Field programmable gate array","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"自律故障補償可能なハードウェアニューロンのバックワードパス演算部の設計","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"自律故障補償可能なハードウェアニューロンのバックワードパス演算部の設計","subitem_title_language":"ja"},{"subitem_title":"Design of Backward-pass Module for Self-defect-Compensatable Hardware Neuron","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","320"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2011-02-25"},"publish_date":"2011-02-25","publish_status":"0","recid":"2494","relation_version_is_last":true,"title":["自律故障補償可能なハードウェアニューロンのバックワードパス演算部の設計"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2025-01-09T05:36:19.198185+00:00"}