{"created":"2023-05-15T09:58:29.865307+00:00","id":2467,"links":{},"metadata":{"_buckets":{"deposit":"175de5f1-a156-49ce-8e89-35a81948978d"},"_deposit":{"created_by":5,"id":"2467","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2467"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002467","sets":["73","73:36","73:36:330","73:36:330:316"]},"author_link":["7152","12503","12078","12506"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"ヒョウジュン CMOS プロセス デ セイゾウ カノウナ タチ SRAM セル ノ セッケイ","subitem_alternative_title_language":"ja-Kana"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-08-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"184","bibliographicPageStart":"177","bibliographicVolumeNumber":"35","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Abstract \nIn this paper, we propose four kinds of multiple-valued SRAM cells can be fa bricated in the standard \nCMOS process. At first, a multiple-valued SRAM cell only using N-channel MOSFETS is presented. \nBecause P-channel MOSFETs are not used in the SRAM cell, the chip area can be reduced. Next, a \nmultiple-v alued SRAM cell with differential circuits is presented. Because the cell i s realized using the \ncurrent-mode inside the cell, multiple thresholds can b e obtained by connecting the wires. The third \nSRAM cell is the circuit cons titution that combined MOSFET with FG-MOSFET. This is realized by \nusing the characteristics of the variable threshold voltage in FG-MOSFETs. The last circuit is a circuit \ncomposition that uses the quantization circuit, and has a high noise margin and a switching sensitivity \ncan be achieved. Because a special fabrication process is not required for realizing all the proposed SRAM \ncells, they can be achieved at a low cost. \nThe proposed multiple-val ued SRAM cells are designed \nwith a 0.35mum CMOS device parameter, and eval uate through HSPICE simulation. As a result, it was \nconfirmed that four pro posal circuits operated as multiple-valued SRAM cells.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山下, 崇","creatorNameLang":"ja"},{"creatorName":"ヤマシタ, タカシ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"12503","nameIdentifierScheme":"WEKO"}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"0000000106573887","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"https://isni.org/isni/0000000106573887"}],"affiliationNames":[{"affiliationName":"宮崎大学","affiliationNameLang":"ja"},{"affiliationName":"University of Miyazaki","affiliationNameLang":"en"}]}],"creatorNames":[{"creatorName":"淡野, 公一","creatorNameLang":"ja"},{"creatorName":"タンノ, コウイチ","creatorNameLang":"ja-Kana"},{"creatorName":"Tanno, Koichi","creatorNameLang":"en"}],"familyNames":[{"familyName":"淡野","familyNameLang":"ja"},{"familyName":"タンノ","familyNameLang":"ja-Kana"},{"familyName":"Tanno","familyNameLang":"en"}],"givenNames":[{"givenName":"公一","givenNameLang":"ja"},{"givenName":"コウイチ","givenNameLang":"ja-Kana"},{"givenName":"Koichi","givenNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"7152","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"50260740","nameIdentifierScheme":"e-Rad_Researcher","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=50260740"}]},{"creatorNames":[{"creatorName":"外山, 貴子","creatorNameLang":"ja"},{"creatorName":"トヤマ, タカコ","creatorNameLang":"ja-Kana"},{"creatorName":"Toyama, Takako","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"12078","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Yamashita, Takashi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"12506","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00004439508.pdf","filesize":[{"value":"713.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00004439508.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2467/files/KJ00004439508.pdf"},"version_id":"ca7a8a9f-5267-44eb-9cd5-55eb4bef44a8"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"SRAM, FG-MOSFET, Differential circuit, Quantization circuit","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"標準CMOSプロセスで製造可能な多値SRAMセルの設計","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"標準CMOSプロセスで製造可能な多値SRAMセルの設計","subitem_title_language":"ja"},{"subitem_title":"Design of Multiple-Valued SRAMs that can be Fabricated by Standard CMOS Process","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","316"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-06-28"},"publish_date":"2007-06-28","publish_status":"0","recid":"2467","relation_version_is_last":true,"title":["標準CMOSプロセスで製造可能な多値SRAMセルの設計"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2024-12-26T07:33:54.451879+00:00"}