{"created":"2023-05-15T09:58:29.821531+00:00","id":2466,"links":{},"metadata":{"_buckets":{"deposit":"4ba4e3a4-afac-494d-8d37-922a609b3201"},"_deposit":{"created_by":5,"id":"2466","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2466"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002466","sets":["73","73:36","73:36:330","73:36:330:316"]},"author_link":["12495","7152","12499","12849","12078"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"コウセイノウ サンプル ホールド カイロ ノ セッケイ ト ソノ オウヨウ","subitem_alternative_title_language":"ja-Kana"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-08-30","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"175","bibliographicPageStart":"169","bibliographicVolumeNumber":"35","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this paper, a new sample and hold circuit (S/H circuit) using a Miller hold capacitance is proposed. In the\nproposed S/H circuit, operational amplifier is not used but an inverter. Therefore, very low power and very small\nchip area can be achieved. Furthermore, the data loss at the tracking condition in the S/H circuit is improved\nby using a double sampling technique with dummy MOS switches. As an application of the proposed S/H\ncircuit, double integrating type A/D converter is designed. The circuits proposed in this paper were evaluated\nthrough Star-HSPICE simulations with O.35μm CMOS devices parameters.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"橋口, 慎吾","creatorNameLang":"ja"},{"creatorName":"ハシグチ, シンゴ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"http://www.isni.org/isni/"}],"affiliationNames":[{"affiliationName":"","affiliationNameLang":"ja"}]}],"creatorNames":[{"creatorName":"桑原, 健介","creatorNameLang":"ja"},{"creatorName":"クワハラ, ケンスケ","creatorNameLang":"ja-Kana"},{"creatorName":"Kuwahara, Kensuke","creatorNameLang":"en"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"淡野, 公一","creatorNameLang":"ja"},{"creatorName":"タンノ, コウイチ","creatorNameLang":"ja-Kana"},{"creatorName":"Tanno, Koichi","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"外山, 貴子","creatorNameLang":"ja"},{"creatorName":"トヤマ, タカコ","creatorNameLang":"ja-Kana"},{"creatorName":"Toyama, Takako","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hashiguchi, Shingo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[{"affiliationNameIdentifier":"","affiliationNameIdentifierScheme":"ISNI","affiliationNameIdentifierURI":"http://www.isni.org/isni/"}],"affiliationNames":[{"affiliationName":"","affiliationNameLang":"ja"}]}],"creatorNames":[{"creatorName":"桑原, 健介","creatorNameLang":"ja"},{"creatorName":"クワハラ, ケンスケ","creatorNameLang":"ja-Kana"},{"creatorName":"Kuwahara, Kensuke","creatorNameLang":"en"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00004439507.pdf","filesize":[{"value":"640.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00004439507.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2466/files/KJ00004439507.pdf"},"version_id":"859fe049-efc8-4fec-a236-a327dff48369"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Sample and hold circuits, Miller hold capacitance, Inverter, Hold erroe, A, D converter","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"高性能サンプル・ホールド回路の設計とその応用","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高性能サンプル・ホールド回路の設計とその応用","subitem_title_language":"ja"},{"subitem_title":"Design of High-Performance Sample-and-Hold Circuits and Its Application","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","316"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-06-28"},"publish_date":"2007-06-28","publish_status":"0","recid":"2466","relation_version_is_last":true,"title":["高性能サンプル・ホールド回路の設計とその応用"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-11-28T04:09:37.642995+00:00"}