@article{oai:miyazaki-u.repo.nii.ac.jp:00002466,
 author = {橋口, 慎吾 and 桑原, 健介 and Kuwahara, Kensuke and 淡野, 公一 and Tanno, Koichi and 外山, 貴子 and Toyama, Takako and Hashiguchi, Shingo and 桑原, 健介 and Kuwahara, Kensuke},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Aug},
 note = {In this paper, a new sample and hold circuit (S/H circuit) using a Miller hold capacitance is proposed. In the
proposed S/H circuit, operational amplifier is not used but an inverter. Therefore, very low power and very small
chip area can be achieved. Furthermore, the data loss at the tracking condition in the S/H circuit is improved
by using a double sampling technique with dummy MOS switches. As an application of the proposed S/H
circuit, double integrating type A/D converter is designed. The circuits proposed in this paper were evaluated
through Star-HSPICE simulations with O.35μm CMOS devices parameters.},
 pages = {169--175},
 title = {高性能サンプル・ホールド回路の設計とその応用},
 volume = {35},
 year = {2006},
 yomi = {ハシグチ, シンゴ and クワハラ, ケンスケ and タンノ, コウイチ and トヤマ, タカコ and クワハラ, ケンスケ}
}