@article{oai:miyazaki-u.repo.nii.ac.jp:00002461,
 author = {大野, 憲司 and Ohno, Kenji and 松本, 寛樹 and Matsumoto, Hiroki and 村尾, 健次 and Murao, Kenji and 村尾, 健次 and Murao, Kenji},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Aug},
 note = {Abstract 
In this paper, switched-voltage (SV) sample/hold (S/H) circuit is presented for low voltage 
operation. The circuit consists of a CMOS SV-delay cell. Thus, the configuration is very simple. 
The proposed circuit can operate using simple nonoverlapping two phase clocks. Performance is verified by simulations on PSpice and using discrete components.},
 pages = {145--149},
 title = {スイッチドボルテージ低電圧サンプルホールド回路},
 volume = {35},
 year = {2006},
 yomi = {オオノ, ケンジ and マツモト, ヒロキ and ムラオ, ケンジ and ムラオ, ケンジ}
}