{"created":"2023-05-15T09:58:24.809329+00:00","id":2373,"links":{},"metadata":{"_buckets":{"deposit":"00107b86-9f67-44d8-a43f-d7cf098d9bdf"},"_deposit":{"created_by":5,"id":"2373","owner":"5","owners":[5],"pid":{"revision_id":0,"type":"depid","value":"2373"},"status":"published"},"_oai":{"id":"oai:miyazaki-u.repo.nii.ac.jp:00002373","sets":["73","73:36","73:36:330","73:36:330:314"]},"author_link":["11805","11812","11807","11815"],"item_10002_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"VHDL ニ ヨル ガクシュウ カノウナ カイソウガタ ニューラル ネットワーク ノ ハードウェア ジッソウ","subitem_alternative_title_language":"ja-Kana"}]},"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2004-10","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"359","bibliographicPageStart":"355","bibliographicVolumeNumber":"33","bibliographic_titles":[{"bibliographic_title":"宮崎大学工学部紀要","bibliographic_titleLang":"ja"},{"bibliographic_title":"Memoirs of Faculty of Engineering, University of Miyazaki","bibliographic_titleLang":"en"}]}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Neural network has been used many applications, such as pattern or image\nrecognition, robot control, optimization problem and so on. However, real-world\nproblems need large scale neural networks, and they lead enormous computation time\nfor training process of neural network. To reduce the· computation time, we try to\nimplement neural network in a FPGA device. In this paper, we discuss on the\nperformance of hardware neural network from the viewpoint of the processing speed\nand the scale of the circuit. The trainable hardware neural network used 117,876 cells\nin FPGA, and it could train the four training patterns in 800ns on the XOR problem.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"宮崎大学工学部","subitem_publisher_language":"ja"},{"subitem_publisher":"Faculty of Engineering, University of Miyazaki","subitem_publisher_language":"en"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00732558","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"05404924","subitem_source_identifier_type":"ISSN"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山森, 一人","creatorNameLang":"ja"},{"creatorName":"ヤマモリ, クニヒト","creatorNameLang":"ja-Kana"},{"creatorName":"Yamamori, Kunihito","creatorNameLang":"en"}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"石田, 二郎"},{"creatorName":"イシダ, ジロウ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉原, 郁夫"},{"creatorName":"ヨシハラ, イクオ","creatorNameLang":"ja-Kana"},{"creatorName":"Yoshihara, Ikuo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ishida, Jiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-06-21"}],"displaytype":"detail","filename":"KJ00002428269.pdf","filesize":[{"value":"415.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"KJ00002428269.pdf","url":"https://miyazaki-u.repo.nii.ac.jp/record/2373/files/KJ00002428269.pdf"},"version_id":"c79e564d-1d20-40d1-a034-5e340a80e79b"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Neural network, VHDL, Hardware implementation, Training","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"VHDLによる学習可能な階層型ニューラルネットワークのハードウェア実装","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"VHDLによる学習可能な階層型ニューラルネットワークのハードウェア実装","subitem_title_language":"ja"},{"subitem_title":"Hardware Implementation of Trainable Multi-Layer Neural Network by VHDL","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"5","path":["73","36","330","314"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2007-06-28"},"publish_date":"2007-06-28","publish_status":"0","recid":"2373","relation_version_is_last":true,"title":["VHDLによる学習可能な階層型ニューラルネットワークのハードウェア実装"],"weko_creator_id":"5","weko_shared_id":2},"updated":"2023-07-30T02:39:25.335324+00:00"}