@article{oai:miyazaki-u.repo.nii.ac.jp:00002373,
 author = {山森, 一人 and Yamamori, Kunihito and 石田, 二郎 and 吉原, 郁夫 and Yoshihara, Ikuo and Ishida, Jiro},
 journal = {宮崎大学工学部紀要, Memoirs of Faculty of Engineering, University of Miyazaki},
 month = {Oct},
 note = {Neural network has been used many applications, such as pattern or image
recognition, robot control, optimization problem and so on. However, real-world
problems need large scale neural networks, and they lead enormous computation time
for training process of neural network. To reduce the· computation time, we try to
implement neural network in a FPGA device. In this paper, we discuss on the
performance of hardware neural network from the viewpoint of the processing speed
and the scale of the circuit. The trainable hardware neural network used 117,876 cells
in FPGA, and it could train the four training patterns in 800ns on the XOR problem.},
 pages = {355--359},
 title = {VHDLによる学習可能な階層型ニューラルネットワークのハードウェア実装},
 volume = {33},
 year = {2004},
 yomi = {ヤマモリ, クニヒト and イシダ, ジロウ and ヨシハラ, イクオ}
}