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oai:miyazaki-u.repo.nii.ac.jp:00002845 2024-12-26T07:33:55Z 73 73:36 73:36:330 73:36:330:323

MOS トランジスタ ノ バックゲート タンシ オ モチイタ コウセイド サンプル ホールド カイロ ノ ケントウ MOSトランジスタのバックゲート端子を用いた高精度サンプル・ホールド回路の検討 Consideration of High Performance Sample-and-Hold Circuit Using Backgate Terminal of MOS Transistor 宮川, 昌士 15009 ミヤガワ, マサシ 酒井, 駿介 15010 サカイ, シュンスケ 田村, 宏樹 7150 タムラ, ヒロキ 90334713 Tamura, Hiroki 外山, 貴子 12078 トヤマ, タカコ Toyama, Takako 淡野, 公一 7152 タンノ, コウイチ 50260740 Tanno, Koichi Miyagawa, Masashi 15014 Sakai, Syunsuke 15015 In this paper, we propose new sample-and-hold circuits, which are low ON-resistance by using backgate terminal of MOSFET. In the proposed circuits, the backgate terminal is used as a control terminal to change the threshold voltage (V_T) of MOSFET. In detail, the backgate is applied to a pulse at the moment of turning on. Using this technique, we can achieve the low ON-resistance. From the evaluation using HSPICE simulation with the 0.35μm CMOS processes parameters, we could confirm that value of ON-resistance decrease about 13% compared with conventional one. departmental bulletin paper 宮崎大学工学部 Faculty of Engineering, University of Miyazaki 2013-08-30 VoR application/pdf 宮崎大学工学部紀要 42 127 134 Memoirs of Faculty of Engineering, University of Miyazaki AA00732558 05404924 https://miyazaki-u.repo.nii.ac.jp/record/2845/files/engineering127-134.pdf http://hdl.handle.net/10458/4724 https://miyazaki-u.repo.nii.ac.jp/records/2845 jpn