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3相クロックを用いた容量比低減型単一利得増幅器構成SC積分器 Capacitance ratio-reduced and unity gain buffer-based SC integrator using three phase clocks 3ソウ クロック オ モチイタ ヨウリョウヒ テイゲンガタ タンイツ リトク ゾウフクキ コウセイ SC セキブンキ 黒木, 伸一 クロキ, シンイチ 松本, 寛樹 マツモト, ヒロキ Matsumoto, Hiroki 松本 マツモト Matsumoto 寛樹 ヒロキ Hiroki 宮崎大学 University of Miyazaki Kuroki, Shinichi Matumoto, Hiroki Three phase clocks, SC integrator, Capacitance ratio In this study, a capacitance ratio-reduced and unity gain buffer-based switched-capacitor integrator using three phase clocks is presented. Principle of operation is described and is also confirmed on SIMetrix. The purpose of this proposal circuit is to decrease the capacitor ratio of the SC integrator, and to improve the maximum frequency that can operate. Very large capacitance ratio is derived. 宮崎大学工学部 Faculty of Engineering, University of Miyazaki 2011-07-30 jpn departmental bulletin paper VoR http://hdl.handle.net/10458/3602 https://miyazaki-u.repo.nii.ac.jp/records/2965 AA00732558 05404924 宮崎大学工学部紀要 Memoirs of Faculty of Engineering, University of Miyazaki 40 111 113 https://miyazaki-u.repo.nii.ac.jp/record/2965/files/21engineering40_pp.111-113.pdf application/pdf 247.2 kB 2020-06-21