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高性能サンプル・ホールド回路とその応用 A High Performance CMOS Sample and Hold Circuit and its Application コウセイノウ サンプル ホールド カイロ ト ソノ オウヨウ 佐藤, 公信 サトウ, キミノブ Sato, Kiminobu 佐藤 サトウ Sato 公信 キミノブ Kiminobu 50260740 淡野, 公一 タンノ, コウイチ Tanno, Koichi 淡野 タンノ Tanno 公一 コウイチ Koichi 宮崎大学 University of Miyazaki 石塚, 興彦 イシズカ, オキヒコ 外山, 貴子 トヤマ, タカコ Toyama, Takako 佐藤, 公信 サトウ, キミノブ Sato, Kiminobu 佐藤 サトウ Sato 公信 キミノブ Kiminobu Ishizuka, Okihiko Sample and hold circuits, Boost circuits, Dummy switch, Hold error, Sigma-delta converters Recently, various portable devices become smaller and smaller, so that the mixed digital and analog LSI is desired to integrate them on a chip. The data converter is an important circuit to realize the mixed digital and analog LSI. The data converter need the conversion time for the quantization and the encode. Therefore, sample and hold (S/H) circuits are necessary to maintain a part of analog information temporarily. However, MOS switches cannot be deeply turned on because enough overdrive voltage cannot be supplied to gates of MOS switches under the low-voltage condition. In this dissertation, the CMOS S/H circuit with the clock boost technique and the input signal tracking technique is proposed. As the results, the proposed circuit reduces the effect of charge injection and feedthrough with maintaining low-voltage, low-distortion and rail-to-rail operation. Next, as an application of the proposed S/H circuit, ΔΣ deta converter is designed. The circuits proposed in this dissertation are evaluated through Star-HSPICE simulations. 宮崎大学工学部 Faculty of Engineering, University of Miyazaki 2005-08 jpn departmental bulletin paper VoR http://hdl.handle.net/10458/378 https://miyazaki-u.repo.nii.ac.jp/records/2406 AA00732558 05404924 宮崎大学工学部紀要 Memoirs of Faculty of Engineering, University of Miyazaki 34 127 134 https://miyazaki-u.repo.nii.ac.jp/record/2406/files/KJ00003579369.pdf application/pdf 1.0 MB 2020-06-21