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下位ビットから変換するオフセット二進数に対応したSC循環型DA変換器
http://hdl.handle.net/10458/4098
http://hdl.handle.net/10458/409847c09929-757b-4dea-96af-4b7110fcf023
名前 / ファイル | ライセンス | アクション |
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engineering41_75-77.pdf (603.6 kB)
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Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 2012-10-26 | |||||
タイトル | ||||||
言語 | ja | |||||
タイトル | 下位ビットから変換するオフセット二進数に対応したSC循環型DA変換器 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Switched-Capacitor Algorithmic DA Converter from Least Significant Bit of Offset Binary Number | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Switched-capacitor, offset binary, DAC, LSB | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
その他(別言語等)のタイトル | ||||||
その他のタイトル | カイ ビット カラ ヘンカン スル オフセット ニシンスウ ニ タイオウ シタ SC ジュンカンガタ DA ヘンカンキ | |||||
著者 |
佐伯, 直哉
× 佐伯, 直哉× 松本, 寛樹× Saeki, Naoya |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In this paper, we propose a switched-capacitor (SC) cyclic digital-to-analog converter (DAC).A proposal circuit performs a DA translation from Least significant bit(LSB), and improves conversion speed. Operation is continued on SIMetrix. The conversion result was obtained in operation conventionally less than a circuit. | |||||
言語 | en | |||||
書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 41, p. 75-77, 発行日 2012-07-30 |
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出版者 | ||||||
言語 | ja | |||||
出版者 | 宮崎大学工学部 | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Faculty of Engineering, University of Miyazaki | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 05404924 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA00732558 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |