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4相クロックを用いた容量比低減型単一利得増幅器構成SC積分器
http://hdl.handle.net/10458/3601
http://hdl.handle.net/10458/36014302216b-2824-4e2c-ab01-1cacf185bcaa
名前 / ファイル | ライセンス | アクション |
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20engineering40_pp.107-109.pdf (310.0 kB)
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Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 2012-03-09 | |||||
タイトル | ||||||
言語 | ja | |||||
タイトル | 4相クロックを用いた容量比低減型単一利得増幅器構成SC積分器 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Capacitance ratio-reduced and unity gain buffer-based switched-capacitor integrator using four phase clocks | |||||
言語 | ||||||
言語 | jpn | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | Switched-capacitor, Four aspect clocks, Capacity ratio reduction, integrator | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
その他(別言語等)のタイトル | ||||||
その他のタイトル | 4ソウ クロック オ モチイタ ヨウリョウヒ テイゲンガタ タンイツ リトク ゾウフクキ コウセイ SC セキブンキ | |||||
著者 |
長倉, 大樹
× 長倉, 大樹× 松本, 寛樹× Nagakura, Hiroki× Matumoto, Hiroki |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In this paper, a novel capacity ratio-reduced and unity gain buffer-based switched-capacitor (SC) integrator using four aspect clocks is presented. Ratio can be reduced to 1/50^3. Operation is also confirmed on SIMmetrics. | |||||
言語 | en | |||||
書誌情報 |
ja : 宮崎大学工学部紀要 en : Memoirs of Faculty of Engineering, University of Miyazaki 巻 40, p. 107-109, 発行日 2011-07-30 |
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出版者 | ||||||
言語 | ja | |||||
出版者 | 宮崎大学工学部 | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Faculty of Engineering, University of Miyazaki | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 05404924 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA00732558 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |